The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A FET includes a gate electrode as a control electrode overlying a semiconductor channel and spaced-apart source and drain regions on opposite sides of the channel between which a current can flow. A gate dielectric layer is disposed between the gate electrode and the channel to electrically isolate the gate electrode from the channel. A control voltage applied to the gate electrode controls the flow of current through the channel between the source and drain regions. The FETs are generally “N” or “P” type FETs, (“nFET” or “pFET”) where the source and drain for nFETs are implanted with “N” type dopants, and the source and drain for pFETs are implanted with “P” type dopants.
A number of challenges arise as feature sizes of FETs and integrated circuits get smaller. For example, significant downsizing of traditional planar FETs leads to electrostatic issues and electron mobility degradation. Scaled-down planar FETS have shorter gate lengths that make it more difficult to control the channel. New device architectures such as nanowires allow further scaling of the integrated circuits, in part because the gate wraps around the channel and provides better control with lower leakage current, faster operations, and lower output resistance. The “gate all around” structure of a FET with nanowires has advantageous short channel characteristics over the electrostatics that the conventional planar FETs or FinFETs provide. Multiple nanowires can be used in the gate of a FET to increase the current capacity. However, there are process challenges in enabling large scale fabrication of nanowire FETs because of the size and structure. Hence nanowire FETs have not been incorporated into current commercial integrated circuit manufacturing.
Accordingly, it is desirable to provide integrated circuits with FETs having nanowires and methods of manufacturing integrated circuits with FETs having nanowires. In addition, it is desirable to provide integrated circuits with FETs using nanowires, where the FETs are manufactured using techniques that allow for further scaling, such as the use of fins and/or replacement metal gates. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.